1. Field of the Invention
This invention relates to a semiconductor device and method for manufacturing same, and in particular relates to a MOS-type transistor with a high withstand voltage.
2. Description of the Related Art
Vertical-type power MOSFETs have been used as devices with high withstand voltages. Important characteristics of a vertical power MOSFET are the on-resistance (Ron) and the breakdown voltage (BVDSS). For a given breakdown voltage of a power MOSFET, a lower on-resistance means higher performance. There is a tradeoff between on-resistance Ron and breakdown voltage BVDSS. The on-resistance of a power MOSFET depends on the resistivity of the electric field relaxation layer (drift region).
FIG. 6 shows the structure of a typical vertical power MOSFET. In the power MOSFET shown in FIG. 6, a drift region 302, which is an electrical field relaxation layer of the same conduction type as the semiconductor substrate 301, is formed on the substrate. This drift region 302 is generally formed by epitaxial growth. A base region 308 is formed by ion implantation and thermal diffusion from the surface of the drift region 302. A conduction type of the base region 308 is opposite to that of the drift region 302. Further, a source region 309 is formed by ion implantation and thermal diffusion from the surface of the base region 308. A conduction type of the source region 309 is opposite to that of the base region 308.
A gate oxide film (gate insulating film) 306 is formed at the surface of the base region 308 between the source region 309 and the drift region 302 on the semiconductor surface. A gate electrode 307 is formed on the gate oxide film 306. A source electrode 311 is formed on the source region 309, and a drain electrode is formed on the rear surface of the semiconductor substrate. The semiconductor substrate 301 and drift region 302 are used as the drain of a MOS transistor. The channel is formed in the base region 308 below the gate oxide film.
In a power MOSFET with such a structure, when there is no gate-source bias applied to the power MOSFET and when a reverse drain-source bias is applied, the depletion layer due to the junction of the drift region 302 and the base region 308 is broadened. Hence no current flows between drain and source (the off state). Since the impurity concentration of the drift region 302 is lower than that of the base region 308, the depletion layer mainly expands on the side of the drift region 302. If the reverse bias voltage is made high and the electric field at the junction becomes equal to or greater than a certain electric field (Ecrit), avalanche breakdown causes a current to flow and results in a breakdown state. The drain-source voltage at Ecrit is BVDSS. FIG. 7 shows the junction between the drift region 302 and base region 308, which is the electric field relaxation layer, and the state at the time of electric field breakdown. If the impurity concentration in the drift region 302 is made low (if the resistivity is raised), the depletion layer during reverse bias is broadened further, and so BVDSS can be raised.
On the other hand, when a voltage is applied to the gate of the power MOSFET so as to turn on the MOSFET, the MOSFET enters the on state. At this time the path of on current flow is through the drift region 302, and so the on-resistance Ron depends on the resistance of the drift region 302. If the impurity concentration in the drift region is raised in order to lower the on-resistance Ron, BVDSS is lowered.
On the other hand, a Superjunction (SJ) structure is known as a structure in which there is no decline in BVDSS even if the resistance of the electric field relaxation layer is lowered. In this structure, by forming a region of conduction type opposite that of the drift region within the drift region, a depletion layer is formed in the drift region. In the technology disclosed in Japanese Unexamined Patent Application Publication No. 2001-298189, after epitaxial growth of Si on an Si substrate, a process of patterning and boron (B) ion implantation to form a p+ region, of conduction type opposite that of the drift region, is repeated a plurality of times.
On the other hand, in T. Henson and J. Cao, “Low Voltage Super Junction MOSFET Simulation and Experimentation”, ISPSD-03 (2003), pp. 37-40, another example of a power MOSFET having a superjunction structure is described. In the technology described in Henson and Cao, a contact hole is formed extending from the substrate surface to the base region, with intermediate insulating film as a mask. In this case, the column region is formed by high-energy ion implantation after formation of the source electrode contact hole.
In a structure disclosed in Japanese Unexamined Patent Application Publication No. 2001-298189, it is necessary to repeat epitaxial growth, ion implantation and heat treatment; and the advantageous results of finer device patterns and substantial improvement in withstand voltage are diminished due to lateral broadening of the column region in consequence of mask alignment precision and thermal diffusion. There is the further disadvantage of increased costs due to the need to perform epitaxial growth a plurality of times. In the structure of Henson and Cao, the mask used in contact hole formation is also used as a mask during high-energy ion implantation, so that the contact hole must be made small. However, if in this structure the contact hole diameter is made smaller than approximately 1 μm, the metal which is to form the electrode (an aluminum alloy is principally used) cannot fill the contact hole interior, so that the on-resistance increases and other problems occur.
As described above, when forming a MOSFET as a conventional semiconductor device, there is the problem that it is difficult to employ finer device design rules while raising the breakdown voltage.